A microprocessor normally includes a program counter for controlling the sequence of executed program steps. The program counter increments through instruction addresses in the order in which they are to be executed. Each program counter output causes an instruction fetch from the program that controls the microprocessor. When a microprocessor is operated by ROM code, the program counter output increments down through the program addresses in the ROM, causing output of a sequence of ROM-contained instructions to the microprocessor for execution. Such a microprocessor is sometimes termed a "mask-programmed" processor. A mask-programmed microprocessor may also employ additional external ROM or downloadable random access memory (RAM).
When a ROM is employed for processor control, techniques are required for the handling of program errors or superseded program sequences. It is known that programs in external ROM/RAM can be more easily updated than a mask-programmed ROM and can further be employed as back-up in case errors are determined in the mask-programmed ROM. Such errors have been handled in the prior art by initially identifying the code within the mask-programmed ROM that is to be superseded. Then, upon reaching an initial code line of the superseded code, a signal is generated to a non-maskable interrupt input of the microprocessor, causing the microprocessor to respond with an interrupt, followed by a branch address. Such an operation requires a number of clock cycles to implement the interrupt state, fetch and execute the branch address, recover from the interrupt state, etc.
Accordingly, it is an object of this invention to provide an efficient means for providing substitute code for superseded ROM code.
It is a further object of this invention to provide a system for providing a substantially seamless jump to substitute code when superseded code is reached in a ROM.